1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a polysilicon gate of a semiconductor device and a method for fabricating the same.
2. Description of the Related Art
In general, along with a continuing trend of scaling down a semiconductor device to achieve higher-integration, the size of a polysilicon gate and the thickness of a gate oxide layer has been rapidly reduced to improve performance of a semiconductor device. As a gate oxide layer gets thinner, ions for increasing conductivity of a polysilicon gate, e.g., boron ions, tend to penetrate into the gate oxide layer sufficiently to vary the threshold voltage and the saturated current. Also, electron depletion tends to increase in the polysilicon gate, as the gate oxide layer gets thinner.
Therefore, it is necessary to increase the doping level of the polysilicon gate to reduce undesired electron depletion in the polysilicon gate. In other words, if the doping level of the polysilicon gate is increased, significant progress can be made in reducing electron depletion. Therefore, in case of a NMOS transistor, a pre-doping process has been proved to bring about a 98% improvement in the level of the electrons in the polysilicon gate.
However, in case of a PMOS transistor, the pre-doping process causes penetration of boron ions into the transistor channel as well as depletion of electrons, which also significantly changes the electrical properties of a semiconductor device.
As shown in FIG. 1, the penetration of boron ions will be described in detail with reference to a conventional PMOS transistor. First of all, a gate oxide layer 30 is formed over a silicon substrate 10. A gate 40 is formed on the gate oxide layer 30. Then, a LDD (lightly doped drain) structure in which the source and drain regions are doped more lightly near the channel is formed on the silicon substrate 10 along with the gate 40 being positioned therebetween. The gate 40 typically is formed of a double layer structure comprising polysilicon layer 41 and silicide layer 43. The silicide layer 43 can be also formed over the source/drain regions.
In the conventional PMOS transistor, a boron ion-implanted layer 42 is formed over the polysilicon layer 41 to be used as a conductive gate. When the pre-doped polysilicon layer 41 is thermally treated, the boron ions from the ion-implanted layer 42 are diffused along the grain boundary of the polysilicon layer 41 at various speeds to thereby penetrate through the gate oxide layer 30 into the transistor channel region of the silicon substrate 10.
Furthermore, even if the doping level of the polysilicon gate increases, there is still a limitation in reducing electron depletion. Further, with the conventional method, the electron level of the polysilicon gate can be increased only up to 92%.
In general, fluorine atoms are known to facilitate the penetration of boron ions through a gate oxide layer into a silicon substrate by enhancing diffusion, which has been disclosed by Ken-ichi Uwasawa and others in a thesis (as shown in 895pp-898pp of IEDM, 1993) titled "Scaling limitations of gate oxide in p+ polysilicon gate MOS structures for sub-quarter micron CMOS devices." This thesis discussed that a p+ polysilicon gate MOS structure is indispensable for sub-quarter micron CMOS devices because of its superior short channel property. However, when BF.sub.2 + ion implantation is performed for doping the p+ polysilicon gate MOS structure, a high temperature annealing process causes a more significant penetration of BF.sub.2 + ions than of B+ ions. Consequently, the penetration of ions degrades the characteristics of MOS devices, especially in terms of controllability of threshold voltage and reliability of the gate oxide layer.
On the other hand, reduction in thickness (Tox) of a gate oxide layer has been accompanied with a continuous scaling of the CMOS device, bringing about significant penetration of BF.sub.2 + ions. For this reason, it is assumed that B+ ions are better for avoiding penetration of ions than are BF.sub.2 + ions.
Yet, it is necessary for small CMOS devices to have shallow source/drain junctions usually formed at the same time with ion implantation of a polysilicon gate. Thus, the polysilicon gate is often doped through an ion implantation process of BF.sub.2 + ions, which may cause significant penetration of BF.sub.2 + ions. In order to block the penetration of the BF.sub.2 + ions, a nitrided gate oxide layer has been proposed. However, there are still a few disadvantages in fabrication of the nitrided gate oxide layer because of its complicated fabrication method and deterioration of hole mobility in a PMOSFET. Therefore, an oxide layer still is a better candidate for gate dielectrics.
For these reasons, there still remains a need to reduce electron depletion and boron penetration to improve the electrical characteristics of MOSFET devices.